A unified and pipelined hardware architecture for implementing intra prediction in HEVC

Jiang, Y.; Llamocca, D.; Pattichis, M.; Esakki, G.

by Y. Jiang, D. Llamocca, M. Pattichis, G. Esakki

Reference:

A unified and pipelined hardware architecture for implementing intra prediction in HEVC (Y. Jiang, D. Llamocca, M. Pattichis, G. Esakki), In IEEE Southwest Symposium on Image Analysis and Interpretation, 2014.

Bibtex Entry:

@INPROCEEDINGS{6806021,
author={Jiang, Y. and Llamocca, D. and Pattichis, M. and Esakki, G.},
booktitle={IEEE Southwest Symposium on Image Analysis and Interpretation},
title={A unified and pipelined hardware architecture for implementing intra prediction in HEVC},
year={2014},
month={April},
pages={29-32},
}