Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF)

Saqib, F.; Dutta, A.; Plusquellic, J.; Ortiz, P.; Pattichis, M.

by F. Saqib, A. Dutta, J. Plusquellic, P. Ortiz, M. Pattichis

Reference:

Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF) (F. Saqib, A. Dutta, J. Plusquellic, P. Ortiz, M. Pattichis), In IEEE Transactions on Computers, volume 64, 2015.

Bibtex Entry:

@ARTICLE{saqib2015pipelined,
	author={Saqib, F. and Dutta, A. and Plusquellic, J. and Ortiz, P. and Pattichis, M.},
	journal={IEEE Transactions on Computers},
	title={Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF)},
	year={2015},
	month={Jan},
	volume={64},
	number={1},
	pages={280-285},
  url={http://ece.unm.edu/ivpcl/Publications/JOURNALS/2015/Pipelined%20Decision%20Tree%20Classification%20Accelerator%20Implementation%20in%20FPGA%20%28DT-CAIF%29.pdf},
	ISSN={0018-9340},}