Dynamically reconfigurable architectures for signal, image, and video processing

By developing hardware architectures for specific signal, image, and video processing operations, it is possible to achieve very high performance while reducing power requirements. There is strong interest in developing efficient architectures for computing fast convolutions and implementing 2D filterbanks for real-time video processing applications. For the most recent research efforts in Dynamically Reconfigurable Architectures, refer to our DRASTIC website .

  1. Carranza, C., Pattichis, M.S., and Llamocca, D., “ Fast and Parallel Computation of the Discrete Periodic Radon Transform on GPUs, Multicore CPUs and FPGAs, ” 25th IEEE International Conference on Image Processing (ICIP), pp. 4158-4162, 2018.
  2. Carranza, C., Llamocca, D., and Pattichis, M.S., “Fast and Scalable Computation of the Forward and Inverse Discrete Periodic Radon Transform,” IEEE Transactions on Image Processing, vol. 25, no. 1, Jan. 2016.
  3. Llamocca, D. and Pattichis, M.S., “Dynamic Energy, Performance, and Accuracy Optimization and Management for Separable 2-D Filtering for Digital Video Processing,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 4, article 30, 30 pages, Jan. 2015.
  4. Jiang, Y. and Pattichis, M.S., “A Dynamically Reconfigurable Architecture System for Time-Varying Image Constraints (DRASTIC) for Motion JPEG,” 17 pages, Journal of Real-time Image Processing, 2014.
  5. Llamocca, D., Pattichis, M., "A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-valued Inputs, Outputs, and Filter Coefficients", VLSI Design, vol. 2014 (2014), Article ID 651943, 24 pages.
  6. Llamocca, D. and Pattichis, M.S., “A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 23, no. 3, pp. 488-502, March 2013.
  7. Llamocca, D., Pattichis, M.S., and Vera, G.A., “Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic,” vol. 2010, 14 pages, International Journal of Reconfigurable Computing, vol. 2010, Article ID 357978, 14 pages, doi:10.1155/2010/357978.

Dynamic arithmetic

In dynamic arithmetic, the goal is to dynamically reconfigure the number, types, and precision of arithmetic cores to provide the most efficient implementations.
  1. Vera, A.G., Pattichis, M.S., and Lyke, J., “A Dynamic Dual Fixed Point Arithmetic Architecture for FPGAs,” International Journal of Reconfigurable Computing, vol. 2011, Article ID 586865, 19 pages, 2011.

Dynamically reconfigurable controller

At UNM, for his M.Sc. thesis, Dr. Colby Hoffman did some early work on elements of the high-speed dynamic partial reconfiguration controller that is currently being used by Xilinx corporation in their products.
  1. Hoffman, C. and Pattichis, M.S., “A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback, International Journal of Reconfigurable Computing, vol. 2011, Article ID 439072, 10 pages, 2011.

Field programmable wiring systems

Field programmable wiring systems generalize FPGAs by allowing automatic routing of different signals. At UNM, we demonstrated field programmable wiring systems that can discover circuit components, build circuits on demand, and maintain circuit operation by dynamically re-routing to maintain operation at all times.
  1. Murray, V., Pattichis, M.S., Llamocca, and Lyke, J., “Field Programmable Wiring Systems,” invited, Proceedings of IEEE, special issue on Reconfigurable Systems: Advanced Applications and Technologies, vol. 103, no. 7, pp. 1159-1180, July 2015.
  2. Llamocca, D., Murray, V., Jiang, Y., Pattichis, M., Lyke, J., and Avery, K., "A Scalable, Open-Source Architecture for Real-Time Monitoring of Adaptive Wiring Panels," AIAA Journal of Aerospace Information Systems, vol. 11, no. 6, pp. 344-358, 2014.
  3. Murray, V., Llamocca, Lyke, J., Avery, K., Jiang, Y., and Pattichis, M.S., “Cell-based Architecture for Adaptive Wiring Panels: A First Prototype,” Journal of the American Institute of Aeronautics and Astronautics, vol. 10, no. 4, pp. 187-208, April 2013.

Reconfigurable systems education

Professor Pattichis led UNM to be one of the first Universities to build reconfigurable computing labs for all levels of the undergraduate and graduate curriculum. UNM also provided Xilinx implemementations of the DSP methods developed by Professor Meyer-Baese in his highly regarded textbook on DSP using FPGAs.
  1. Meyer-Baese, U., Vera, A., Meyer-Baese, A., Pattichis, M. and Perry, R., “An Undergraduate Course and Laboratory in Digital Signal Processing with Field Programmable Gate Arrays,” IEEE Transactions on Education, vol. 53, no. 4, pp. 638-645, Nov. 2010.
  2. Kief, C. J., Pattichis, M.S., Pollard, L.H., Vera, G.A. and Parra, J.E., “An XUP-UNM Educational Platform – A Dual FPGA Platform for Reconfigurable Logic,” Computer Applications in Engineering Education, Wiley Interscience, vol. 17, no. 2, pp. 232-239, June 2009.
  3. "Educational Uses of FPGAs," D. Bouldin, Ed., short (< 1 page) invited article describing UNM's labs, cites authors M.S. Pattichis, H. Pollard., J. Parra, A. Vera, A., and C. Kief as "driving Personnel," IEEE Circuits and Devices Magazine, pp. 4, Sept / Oct 2004.

Other architecture papers

  1. Saqib, F., Dutta, A., Plusquellic, J., Ortiz, P., and Pattichis, M.S., “Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF),” IEEE Transactions on Computers, vol. 64, no. 1, pp. 280-285, Jan. 2015.

Commercialization

Please refer to the ivPCL commercialization webpage.