Partial Reconfiguration on ZedBoard using Xilinx Tools
Partial Reconfiguration has the ability to reconfigure part of the FPGA device while the rest of the device continues to operate. The advantages of using PR is it can be used to reduce power consumption and save hardware resources.
Figure. Basic Premise of Partial Reconfiguration on ZedBoard
Get Started Tutorial on Partial Reconfiguration using Vivado
PR_Tutorial by Nishmitha Naveenchandra Kajekar from Marios Pattichis on Vimeo.
Partial Reconfiguration is the modification of an operating FPGA design by loading a partial configuration file which will reduce configuration time and save memory. This is a Tutorial by Xilinx which is been modified so as to be implemented on ZedBoard. The objetive of the Tutorial is to implement a project that can be dynamically reconfigured using the Zed Board and also learn the Partial Reconfiguration (PR) flow with the Vivado TCL console.
Vivado Partial Reconfiguration Documentation from Xilinx
- UG909:Vivado Design Suite User Guide on Partial Reconfiguration
- UG947: Vivado Design Suite Tutorial on Partial Reconfiguration